| 摘要 |
<p>PURPOSE:To prevent the generation of erroneous operation output of a CPU by adding a time-up signal use F/F (hereinafter, a time-up FF) to a timer processing device, and controlling the updating of a time-up signal from the CPU. CONSTITUTION:A timer processing device 2 is connected to a CPU1, and a counting data 9 and a time-up signal are obtained by supplying a time limit value setting data 8 to said device. In such a case, a time-up FF10 operated by a time-up control signal 11 is added to the timer processing device 2. In such a state, said CPU1 sets a time limit value to a subtracting counter 4, and sets a start FF6. Said processing device 2 feeds a clock pulse 3 to the subtracting counter 4 from the first AND circuit 12 under the condition that a time-up FF7 is not being set, and ''1'' count is subtracted. Zero of the counting data 9 of this counter 4 is detected, and the time-up FF7 is set, by which an FF value of a time-up FF10 is updated by inputting said time-up control signal 11.</p> |
