| 摘要 |
PURPOSE:To prepare easily a debug monitor by providing a mechanism for assigning the information for a control to an instruction and a specified bit of a status register, and generating an interruption before executing the instruction. CONSTITUTION:When an instruction to be executed is fetched, and set to an instruction register 31, B bit information of the register 31 is supplied to an AND gate 34 together with BE bit information and inverted BE bit information of a status register 32. In said gate, an AND condition is gained, and its result is supplied to an interrupting circuit, and also an instruction decoding circuit through an invertor 35. If an output of the AND gate 34 is ''HIGH'' level, an output of the invertor 35 becomes ''LOW'' level, and only the interrupting circuit is driven. On the contrary, if the output of the AND gate 35 is ''LOW'' level, only the instruction decoding circuit is driven. Also, in this case, an output of the AND gate 34 is fed back to BM bit of a status register 22, and the interruption generating condition is controlled.
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