| 摘要 |
PURPOSE:To widen an application range of a digital pattern generator by making an inhibiting signal ineffective with regard to a desired bit in a digital pattern output of a parallel bit. CONSTITUTION:An external inhibiting signal of a terminal 32 is inverted selectively by a multiplexer (MUX)36, and an OR gate 28 and an AND gate 30 derive OR and AND of an internal inhibiting signal and an external inhibiting signal. Subsequently, by an MUX26, the internal inhibiting signal, the external inhibiting signal, and their OR and AND are selected, and can be made an inhibiting signal which is common to each bit of a parallel digital signal, therefore, it can be applied to various test conditions. In accordance with a connecting state to a processor system to be tested of output terminals 48-54, a mask signal from a control circuit 38 is set. For instance, when a mask signal to NAND gates 40, 42 is set to a ''high'' level, and a mask signal to NAND gates 44 and 46 is set to a ''low'' level, the inhibiting signal is made ineffective with respect to a signal from terminals 52, 54. |
