| 摘要 |
PURPOSE:To attain the double precision multiplication with a simple operation by dividing a multiplier X having a double precision degree of (2n-1) bits into an high-order word XM with subtraction of upper (n) bits and a low-order word XL with subtraction of low-order (n-1) bits and ''0'' added to the highest place respectively. CONSTITUTION:The low-order words of a double precision degree stored in a register 26-1 are selected by a word selecting circuit 27 and supplied to a single precision multiplier 22. While the low-order words stored in a register 26-2 are supplied to the multiplier 22. The high-order words of the register 26-2 are supplied to the multiplier 22. At the same time, the output of the multiplier 22, i.e., the result of multiplication of low-order words is supplied to a register 26-3 via a selection circuit 24 with no addition carried out by a double precision ALU25. The high-order words of the register 26-1 are supplied to the multiplier 22. At the same time, the output of the multiplier 22, i.e., the result of multiplication of low-order words and hih-order words of a double precision multiplicand is supplied to a register 26-4 as it is via the circuit 24 with no addition carried out by the ALU25. The low-order words of the register 26-2 are selected by the circuit 24 and supplied to an input register 22-2. |
