发明名称 APPARATUS FOR TESTING LOGIC CIRCUIT
摘要 PURPOSE:To make it possible to rightly perform the extraction of data only by bringing the leading end of a probe into contact with the test point of a circuit to be tested, by providing H- and L-levels detection comparators, an intermediate level detection means and a control means. CONSTITUTION:The input signal imparted from a probe 2 is guided to an H- level detection comparator 51 and an L-level detection comparator 52 and further guided to a data sampling latch 54. The signal input terminals of the comparators receive voltages +V, -V through resistors R1, R2 so as to be brought to the intermediate value of H- and L-levels when the probe 2 is opened and the outputs of the comparators 51, 52 are inputted to a gate 53. The latch 54 receives even the output of the gate 53 along with the comparators 51, 52 and, every when the sample clock is imparted from a control circuit 10, latches input data. Then, a test routine is conducted by the circuit 10 to impart a test pattern. Next, the circuit 10 compares pick-up data and good product quality to perform quality judgement and, in the case of inferiority, a display device 11 displays an inferior place.
申请公布号 JPS60228972(A) 申请公布日期 1985.11.14
申请号 JP19840085220 申请日期 1984.04.27
申请人 YOKOKAWA HOKUSHIN DENKI KK 发明人 YOSHIDA YOSHIO
分类号 G01R31/28;G06F11/22 主分类号 G01R31/28
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