| 摘要 |
PURPOSE:To fine the pitch width of a memory cell and memory itself by connecting a first conduction type wiring section to a drain and a gate through an insulating film on the gate and connecting a second conduction type wiring section to the drain through said insulating film. CONSTITUTION:Gate electrodes 57 are formed by first layer polycrystalline silicon containing a first conduction type impurity, and a second layer polycrystalline silicon wiring section 62a containing the first conduction type impurity is shaped on a first layer inter-layer insultaing film 59 coating the gate electrodes 57, and connected to a first conduction type drain region and the gate electrodes through a contact hole 61. A second layer polycrystalline silicon wiring section 63a containing a second conduction type impurity is shaped on the inter-layer insulating film while being connected to said wiring section, and connected to a second conduction type drain region 55 through a contact hole 61. |
