| 摘要 |
PURPOSE:To obtain a correct count result while maintaining the advantage of an asynchronous counter by adding the asynchronous counter as an auxiliary counting circuit to a counting circuit which uses an asynchronous counter. CONSTITUTION:The auxiliary counting circuit 11 composed of the asynchronous counter is added to the counting circuit 10 composed of the asynchronous counter. A clock signal 2 is supplied to the circuit 11 as well. The circuit 10 counts the clock with a gate signal 4. At this time, the circuit 11 is reset. Then, the gate of the circuit 10 is closed with the gate signal 4 to stop its counting operation and the circuit 11 is released from being reset and begins to count. The circuit generates a latch signal 12 at some value. A holding circuit 7 inputs the count output 6 of the circuit 10 with this signal 12 and a circuit 9 performs specific operation with the holding circuit output 8. For the purpose, a setting is so made that the generation of the signal 12 is delayed by more than the time from the count stop of the circuit to when the correct count output is obtained, and then the deficits of an asynchronous system are removed and the advantage is utilized.
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