发明名称 Double precision multiplier.
摘要 <p>A double precision multiplier includes 2's complement single precision multiplication means responsive to two input data, each of which has a predetermined word length of n bits as single precision data, for performing the multiplication of the two data to produce one (2n-1 )-bit double precision data; double precision register means having plural double precision registers for storing the double precision data from the multiplication means into one of the registers specified by a first external control signal; word selecting means responsive to a second external control signal for selecting either one single precision data obtained by taking out the upper word of the double precision data stored in one of the registers or one single precision data obained by adding one "0" bit before the most significant bit (MSB) of the remaining lower word of the double precision data stored in one of the registers; shift means for shifting the one single precision data selected by the selecting means to convert it to one double precision data by expanding the MSB of the single precision data; and double precision arithmetic and logic operation means for executing an arithmetic and logic operation of the double precision data with the MSB expanded and the double precision data stored in one of the registers to produce a result of the arithmetic and logic operation to the register means.</p>
申请公布号 EP0161089(A2) 申请公布日期 1985.11.13
申请号 EP19850302908 申请日期 1985.04.25
申请人 NEC CORPORATION 发明人 KURODA, ICHIRO C/O NEC CORPORATION;NISHITANI, TAKAO C/O NEC CORPORATION;TANAKA, HIDEO C/O NEC CORPORATION;KAWAKAMI, YUICHI C/O NEC CORPORATION
分类号 G06F7/76;G06F7/533;G06F7/00;G06F7/52;G06F7/53;(IPC1-7):G06F7/52 主分类号 G06F7/76
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