发明名称 Fabrication method for controlled via hole process
摘要 A method for forming via holes having a rounded sidewall profile includes exposing a layer or organic positive photoresist to a formic gas plasma while the surface of the photoresist layer is bombarded with ions and electrons in a high voltage biased environment in which the photoresist layer is capacitively coupled. The photoresist layer may be exposed to UV light either before or after the formic gas plasma step.
申请公布号 US4552831(A) 申请公布日期 1985.11.12
申请号 US19840576991 申请日期 1984.02.06
申请人 INTERNATIONAL BUSINESS MACHINES CORPORATION 发明人 LIU, CHENG-YIH
分类号 G03F7/00;G03F7/20;G03F7/26;G03F7/38;H01L21/027;H05K3/00;(IPC1-7):G03C5/00;B05D3/06 主分类号 G03F7/00
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