| 摘要 |
PURPOSE:To simplify the circuit configuration of a 2/3-frequency dividing circuit and to digitize the entire circuit, by constituting the 2/3-frequency dividing circuit of an 1/3-frequency dividing circuit, shift register, and logic circuit. CONSTITUTION:An input pulse (a) having a duty of 1:1 from the input terminal 1 of a 2/3-frequency dividing circuit is inputted in an 1/3-frequency dividing circuit 2 and the circuit 2 outputs a pulse (b) whose ratio of high level period to low level period is 2:1. The pulse (b) is inputted in the 1st shift register 3 and triggered by the positive leading edge of the pulse (a) from a clock terminal CK, and then, a pulse (c) is inputted in the 2nd shift register 4 and triggered by the negative leading edge of the pulse (a) from the clock terminal CK, and then, a pulse (d) is outputted from the output terminal Q of the register 4. The AND of the pulse (d) and the pulse (b) from the circuit 2 is taken at an AND circuit 5 and a pulse (e) whose frequency is divided into 2/3 is outputted to an output terminal 6. Thus the entire circuit of the 2/3-frequency dividing circuit is digitized and the circuit configuration is simplified.
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