| 摘要 |
<p>PURPOSE:To obtain a proper timing and to apply the timing to a timing signal regenerating circuit with a simple circuit configuration, by superimposing a received signal, a signal obtained by delaying the received signal by one bit, and another signal obtained by delaying the delayed signal further by one bit upon each other. CONSTITUTION:A received signal 22 from the input terminal 21 of a timing regenerating circuit is delayed by 1/2 bit T0 at a delay circuit 23 and an output 25 is outputted from a logical negation circuit 24, and then, the AND of the signal 22 and output 25 is taken at an AND circuit 26. The output 27 of the circuit 26 is supplied to an OR circuit 28 and, at the same time, branched to a delay circuit 29 where the output 27 is delayed by one bit 2T0. The delayed output 30 is inputted in the circuit 28. Moreover, the output 30 of the circuit 29 is branched to a delay circuit 31 where the output 30 is delayed by one bit 2T0 and the delayed output 32 is inputted in the circuit 28 where the OR of the output 27 of the circuit 26 and the output 30 of the circuit 29 is taken. Then a timing signal 33 is outputted from an output terminal 34. Thus the constitution of the timing regenerating circuit is simplified.</p> |
