| 摘要 |
PURPOSE:To suppress the change in the frequency characteristic of a CCD due to a clock frequency by using a linear phase equalizer circuit comprising other CCD controlled by the clock frequency to compensate the change in the frequency characteristic of one CCD due to the clock frequency. CONSTITUTION:Output signals from delay elements 1, 6, 7 are given to an adder/ substractor circuit 8 where they are added/subtracted by a prescribed adding ratio in the delay element 1 driven by the clock signal generated from a voltage controlled oscillator 3 and transmitting a signal with sample-and-hold operation, the delay element 6 delaying the output signal of the delay element 1, and the delay element 7 delaying the output signal of the delay element 6. Then the delay elements 6, 7 are controlled by the same or equivalent signal as and to he clock signal. The frequency characteristic of an information delay equipment is improved by providing the linear phase equalizer circuit 2 through the constitution above after the delay element 1. |
