发明名称 SYNCHRONIZING SEPARATOR CIRCUIT
摘要 PURPOSE:To realize easily circuit integration with a few adjusting processes of the titled circuit by constituting the circuit separating a synchronizing signal included in a television signal as a logic circuit. CONSTITUTION:When a signal A is inputted to a shift register 10 shifted by a clock Cp1, the signal is shifted at each stage. Shift outputs of each stage are ANDed and an output F is inputted to a frequency division circuit 12 via inverters 11a, 11b. The signal is frequency-divided into three and an output G is obtained, an output H ANDed with an output F is inputted to other terminal of a flip-flop to which the signal H is applied. A pulse width signal I from the leading of the output H till the rising of the signal A is obtained as an output P.L. Moreover, a frequency division circuit 14 makes control so that no excess pulse is outputted.
申请公布号 JPS60226208(A) 申请公布日期 1985.11.11
申请号 JP19840081707 申请日期 1984.04.25
申请人 HITACHI SEISAKUSHO KK 发明人 ISHIBASHI SUSUMU
分类号 H03L7/00;H03K5/00 主分类号 H03L7/00
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