| 摘要 |
PURPOSE:To always obtain a good digital signal by generating a clock signal synchronizing with rise and fall, respectively, of an outputted digital signal, and setting a binary-coded reference level in accordance with the difference in phase of these clock signals. CONSTITUTION:When a binary-coded reference level Vth supplied to a negative terminal of a comparator 6 with respect to a reproducing data signal SDATA supplied to its positive terminal, a digital signal SD having no error is obtained from the output side of the comparator 6, pulse signals P1 and P2 are obtained from a monostable multivibrators 71 and 72, and also clock signals CLK1 and CLK2 are obtained from PLL circuits 81 and 82. Accordingly, the clock signals CLK1 and CLK2 are equal in phase, and the reference level Vth maintains its value as it is. On the other hand, when the binary-coded reference level Vth is not correct, an erroneous digital signal SD is obtained, and the pulse signals P1 and P2, and the clock signals CLK1 and CLK2 are obtained, respectively. Accordingly, the clock signals CLK1 and CLK2 are different in phase with each other, a down signal Sdown is supplied to a charge pump 10, the reference level Vth is controlled, and a digital signal having no error is obtained. |
