| 摘要 |
PURPOSE:To reduce the circuit scale of a DAC by applying the period of a half period of a frequency signal of two times of a sampling frequency inputted to the DAC, to an integral capacity discharge period and a sampling signal period, respectively, and inputting a signal of two times or four times of the sampling frequency to the DAC. CONSTITUTION:A DAC110 receives signals of 123-125 from a digital filter circuit 113, sets a discriminating terminal 119 to a GND level when the prestage is inserted into a digital filter, and it is provided with two integrators, executes, integration of one channel in a period in which the signal of 124 is ''LO'', executes integration of the other channel in the period of a half period of ''HI'', and uses two channels in common by providing only one set of current source. Also, an integral capacity discharge period and a sampling period of a sample holding circuit of the post-stage are set to the period of a half period of the frequency signal 125 of two times of right and left discriminating signals, by which it is possible to obtain a system which can always generate easily a suitable integral capacity discharge period and a sampling period, even if a sampling period and a master clock frequency are varied. In such a way, a digital filter LSI and a DACIC small in circuit scale can be realized. |
