发明名称 TIMING GENERATING CIRCUIT
摘要 PURPOSE:To output one timing signal without level loss from a timing signal incoming at random with simple constitution by constituting the circuit of a transmission gate MOSFET and a bootstrap boosting circuit. CONSTITUTION:With a timing signal OE0 at a high level, when a Q32 of a transmission gate is turned on via an MOSFETQ31 and a timing signal phiOP reaches a high level before a delay signal OE1 of the signal OE0 goes to a high level, the signal phiOP is boosted by the self-bootstrap operation of the capacitance between the gate and channel of the Q32 and outputted as a timing signal phiOP'. On the other hand, when the signal OE1 goes first, the signal phiOP is boosted by a bootstrap capacitor CB2 connected to the gate of the Q32, outputted as the signal phiOP', and when the signal phiOP takes precedence over the OE0, the bootstrap is applied with a delay similarly. Then one timing signal is outputted without level loss among timing signals incoming at random with simple constitution.
申请公布号 JPS60224192(A) 申请公布日期 1985.11.08
申请号 JP19840078469 申请日期 1984.04.20
申请人 HITACHI SEISAKUSHO KK 发明人 KINOSHITA YOSHITAKA;OKADA JIYOUJI
分类号 G11C11/407;G11C11/34;(IPC1-7):G11C11/34 主分类号 G11C11/407
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