| 摘要 |
PURPOSE:To suppress easily the occurrence of an intermediate level and a through current by providing two transistors TRs having opposite polarities whose sources and drains are connected to gates of two complementary output TRs. CONSTITUTION:When a signal A is ''1'' and a signal B is changed from ''1'' to ''0'', outputs O1 and O2 of an NAND gate 1 and an NOR gate 2 are changed from ''0'' to ''1'' after a prescribed time. A prescribed time after this change, a gate potential O2' of a TrQN reaches thresholds of an inverter IV5 and the TrQN. At this time, the IV5 is changed from ''1'' to ''0'', and therefore, a P- channel TrQP' is turned on, and a potential O1' becomes ''1'' quickly, and the TrQP is turned off. Thereafter, though the N-channel TrQN is turnen on, the intermediate level does not appear in an output terminal O3 and the through current is not generated because the TrQP is turned off. When the signal A is changed from ''1'' to ''0'', the intermediate level and the through current are not generated because Trs QN and QP are changed to the turn-off state. |
