发明名称 MODULATION CIRCUIT OF DIGITAL PULSE WIDTH
摘要 PURPOSE:To prevente the generation of an undesired pulse and to obtain a PWM output with high accuracy by synchronizing the generation timing of the output pulse of a pulse synthesizing means with a non-trigger point of a reference clock pulse. CONSTITUTION:A pulse generator 4 produces a quantum pulse, and a digital data output circuit 6 produces the data to be converted with plural bits. This data and the quantum puls are ANDed every bit and are supplied to a delay circuit 20. The circuit 20 is triggered at a non-trigger point, i.e., a rise point of a reference clock pulse fin. As a result, the PWM output produced at an output terminal 24 is delayed by an amount equal to a pulse width of the fin. This can avoid the hazard.
申请公布号 JPS60223227(A) 申请公布日期 1985.11.07
申请号 JP19840078892 申请日期 1984.04.18
申请人 ROOMU KK 发明人 SAWAMURA AKIRA
分类号 H03K5/00;H03K5/1252;H03M1/82 主分类号 H03K5/00
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