| 摘要 |
PURPOSE:To eliminate the need to divide the edge detection pulse width of an input signal accurately into half by using two flip-flops and two switch circuits controlled by the outputs of said flip-flops to constitute controlled by the outputs of said flip-flops to constitute a phase comparator. CONSTITUTION:When the phase of a clock C is advanced, the width of a positive voltage pulse is reduced for the output P of a phase comprator 5. Then the reduced pulse width is integrated by an LPF2. Thus the output voltage is reduced and the oscillation frequency of a voltage control oscillator 3 is lowered. This lowered oscillation frequency is divided by a frequency divider 4. Thus the phase of a clock C is delayed and phase-locked correctly. Under such conditions, the time coincidence is secured between the rise or fall edge of an input I and the rise of the clock C. Then the pulse width of the positive voltage of the output P is equal to the pulse width of the negative voltage. Thus the oscillator 3 oscillates signals of a fixed frequency. |
