TIMING EXTRACTION CIRCUIT

摘要

PURPOSE:To extract a timing signal which is free from jitter by counting the difference between leading and lagging pulses fed from a circuit which compares the rise or fall phase of a bipolar signal with a reference signal. CONSTITUTION:The rise and fall phase comparators 3-1 and 3-2 compare the rise and the fall of a pulse waveform (b) with a reference clock pulse (c). Then pulses d1u and d1d are outputted when the rise phase is led and lagged respectively. While pulses d2u and d2d are produced when the fall phase is led and lagged respectively. The output of an OR gate 4-1 increases the count value of an up-down counter 5; while the output of an OR gate 4-2 decreases the count value of the counter 5. Then pulses gD and gU are produced when the counter 5 has the count value larger and smaller than a fixed level, respectively. These pulses are supplied to a pulse loading/unloading circuit.