| 摘要 |
PURPOSE:To obtain an ultramicroscopic and high withstand voltage transistor having the alleviated concentration effect of a drain electric field and improved withstand voltage between a gate and a drain or between a gate and a source by a method wherein the interval between the gate and the drain of a high impurity density region and a silicide region is made wider than the interval of other drain regions. CONSTITUTION:After a gate side wall insulating film 5 has been formed, a low impurity density source region 7 and a drain region 8 are formed on a silicon thin film part. Subsequently, a titanium silicide (TiSi2) 11 and 12 are formed on the silicon thin film surface only which is selectively exposed on the source and the drain regions. When a non-reaction titanium film is removed using hydrogen peroxide solution (H2O2) under the above-mentioned condition, TiSi2 layers 11 and 12 are selectively left on source and drain low impurity density regions 7 and 8 only. When heat treatment under resistance state is performed after the above-mentioned TiSi2 layer has been formed and left, layers 9 and 10 of approximately 10nm in thickness having the surface impurity density of 5X10<19>cm<-3> is deposited on the surface part of the source and drain low impurity density regions 7 and 8 having the surface impurity density of 5X10<18>cm<-3> before performance of the low-resistance-state-forming heat treatment. |
