| 摘要 |
<p>PURPOSE:To prevent data errors by inputting an output from register in parallel with a parallel/serial converting circuit with a timing signal in synchronization with a burst signal to control the circuit thereby decreasing the phase difference of both parallel inputs. CONSTITUTION:A low-speed clock CLK-L and a universal signal phase signal PH are inputted both to a timing generating circuit 6. The timing generating circuit 6 consists of a shift register and generates two kinds of timing signals. The two kinds of the timing signals are shifted mutually by N/2 bits. A phase comparison circuit 5 compares the two kinds of timing signals generated by the timing generating circuit 6 with the phase in a burst signal phase signal PH' and controls changeover switches 7, 8 to select a larger phase difference more than a specified value. That is, a signal (2) is transferred from a register 3 to a converting circuit 4 by using the burst phase signal PH' through the timing signal (4) in the figure, arranged into a prescribed location by a high speed clock CLK-H and becomes a burst signal and then is outputted to an output terminal OUT.</p> |
