CLOCK CONTROLLED ANTI-BLOOMING FOR VIRTUAL PHASE CCD'S

摘要

An anti-blooming structure for virtual phase CCD imaging arrays is presented in which a fixed anti-blooming potential barrier and charge overflow drain is built in, not requiring any additional overlying MOS gate. The unique feature of the virtual phase CCD, that it requires only a single MOS gate level for charge transport and storage is thus preserved, which is reflected in high yield and high performance of the anti-blooming CCD array imagers. The anti-blooming structure comprising an anti-blooming barrier and overflow drain replaces every second channel stop in a regular imaging array following thus normal operation of the virtual phase CCD and at the same time the removal of the excess charge from the array channel via the overflow drains.