| 摘要 |
PURPOSE:To produce a PLL with a gate circuit without using a coil by smoothing the output of a switch circuit that switches alternately the outputs of the 1st and 2nd frequency dividers with the output of an exclusive OR circuit as well as the output of an exclusive OR circuit to which the output of said switch circuit and an FS signal are supplied. CONSTITUTION:A reference clock 4 is divided by 1/m and 1/n frequency dividers of a PLL12 respectively, and these divided clocks are supplied to AND gates 7-1 and 7-2 of a switch circuit 7. The outputs of both gates are supplied to an EXOR gate 9 via an OR gate 7-4 and a 1/P frequency divider 8. When a signal of a high frequency is supplied to the gate 9 via an input terminal 3, the signal is delivered from the gate 9 by the clocks divided down to 1/P and 1/n respectively. This output of the gate 9 is converted into frequency voltage f/V via an LPF10 and delivered through an output terminal 11.
|
