发明名称 MULTIPLYING CIRCUIT FOR FLOATING POINT DATA
摘要 PURPOSE:To detect speedily whether postnormalization is performed or not by forecasting and detecting the output of a carry propagation adder by using the final sum output and carry output of a carry holding adder tree and the output of a carry look-ahead circuit. CONSTITUTION:An AND circuit 831 outputs ''1'' only when respective bits are ''00'' or ''11'' and a carry from the carry look-ahead circuit 82 is ''0'' because the NOT output of EOR as to respective high-order one-digit bits is outputted from a half-adder 81; one of two conditions required for postnormalization is detected and an AND circuit 832 detects the other condition similarly. Then, an AND circuit group 84 outputs ''0'' only when the sum of one of bits 1-3 of high-order one-digit bits 1-3 and a carry are ''11'', to block the circuit 831 and 832, so this functions to remove one of two condition cases which corresponds to bits ''11''. Thus, whether the postnormalization is performed or not is detected.
申请公布号 JPS60222931(A) 申请公布日期 1985.11.07
申请号 JP19840079404 申请日期 1984.04.20
申请人 FUJITSU KK 发明人 MIYANAGA HIDEO
分类号 G06F7/487;G06F5/01;G06F7/00;G06F7/506;G06F7/508;G06F7/53;G06F7/76 主分类号 G06F7/487
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