| 摘要 |
PURPOSE:To reduce the production cost of a digital phase synchronization circuit by applying pulse width modulation to a reference clock according to the phase shift and using the reference clock of a Baud rate N part to perform correction every 1/N-bit length. CONSTITUTION:A phase comparator 2 samples the outut signal A of a code conversion point extracting circuit 1 and a synchronizing clock CLK to 2-step shift registers 2-a and 2-b with a phase -phi1. A phase advance/delay deciding circuit 2-C decides the lead/lag in phase according to the clock preceding by a sampling cycle and the sampling state of this time and outputs a signal to a pulse width modulating circuit 7. When the phase of the CLK is advanced, the circuit 7 outputs a signal to an N/2 dividing counter so that the CLK is extended by the 1/N-bit length. While the counter is controlled in the same way to shorten the CLK by 1/N bits if the phase of the CLK is delayed. |
