| 摘要 |
PURPOSE:To markedly improve the degree of integration, to accomplish the stabilization of the potential of wells and a source, and also to enable to perform a high speed operation of the titled semiconductor device by a method wherein the number of wirings and contact holes required on the circumference of the wells are reduced. CONSTITUTION:n-Wells 261, 262... are provided on the main surface of a semiconductor base consisting of a p type silicon substrate 21 and a p type silicon layer 23, an n<+> type wiring layer 24 which comes in contact with said n-wells 261, 262... is provided in the internal part of the above-mentioned semiconductor base, and a p-channel MOS transistor, consisting of oxide films 281, 282..., gate electrodes 291, 292..., and n<+> type source regions 311, 312... is formed on the above-mentioned wells 261, 262.... Besides, through holes 351, 352... reaching said n<+> type wiring layer are perforated on the wells 261, 262..., a potential transfer paths 371, 372..., consisting of polycrystalline silicon containing n type impurities, are formed in said through holes 351, 352... and a structure, wherein Al electrodes 401, 402... with which said potential transfer paths 371, 372... and source regions 311, 312... will be connected common through the intermediary of contact holes 39... are provided on a CVD-SiO2 film 38, is obtained. |
