| 摘要 |
PURPOSE:To curtail remarkably the number of parts by arbitrating the competition of a bus, and holding easily one set of common memory in common between plural microprocessors. CONSTITUTION:When a use request signal of a common memory is inputted to a line 41, a use permitting signal of the common memory is not outputted from an AND gate 64 unless an output of a decoder 63 is outputted. Thereafter, when an output of a binary counter 62 is changed, and an output appears in the decoder 63, an output of the gate 64 becomes a use permitting state of the common memory. On the other hand, this output changes an output of a multi-input NOR gate 67, therefore, an AND gate 61 stops passing of a clock, stops an operation of the binary counter 62, and the decoder l63 continues its output. Thereafter, when a CPU1 completes a memory cycle, and makes a use request of the common memory ineffective, it is transmitted to the multi-input NOR gate 67 and the AND gate 61, and the gate 61 makes a clock of a clock generator 60 pass to the counter 62. |
