| 摘要 |
<p>1. A circuit for decoding a television signal which, at the time of transmission, has been encoded for each line by pseudo-random shift of the video signal (21) in relation to the line sync signal (20), said decoding circuit comprising a delay line (12) of the charge transfer type (DTC), whose delay is controlled in order to reestablish the correct shift between the sync signal and the image signal, and a switch (13) controlled in such a way that the line sync signal (20) passes along a branch path (14), characterized in that the delay line has a capacity near that of one line of the video signal of the duration P, the frequency of the clock signal for the control of this line (DTC) is such that a video line is delayed by a value of P1 -B, of the same order of magnitude as the duration P of a video line, and the decoding circuit comprises a means (18 and 19) to lock the clock signal, or to diminish the frequency of such clock signal, during a time which, for each line, is a function of the shift to be effected.</p> |
