| 摘要 |
PURPOSE:To prevent lag in synchronism, to simplify a circuit configuration, and to make computer control easy, by counting horizontal synchronizing signals with the counter for counting pulses of the repeated frequencies of multiple of the horizontal synchronizing signals. CONSTITUTION:An 11-bit counter 50 generates eight pieces of address information in one horizontal scanning period and accesses addresses of memories 51a and 51b. The memories are caused to generate a prescribed pieces of horizontal deflection data and two pieces of vertical deflection data in one horizontal scanning period correspondingly to the addresses. Moreover, when several high-order bits of the counter 50 are decoded by means of a decoder 52, a linear cathode driving pulse can be obtained synchronously. |
