| 摘要 |
PURPOSE:To obtain a synchronizing clock generating circuit having no high frequency output by compensating a lower limit of a pulse width of an output level where a high frequency output might be generated to a specific setting value. CONSTITUTION:The titled circuit consists of an original oscillation circuit 1 oscillating a frequency being (m) times of a desired clock frequency, a synchronous counter 2 with a reset terminal, an auxiliary counter 3 for counting pulse width and an OR circuit 4. The lower limit of the pulse width is compensated by the auxiliary counter 3. When a load terminal 8 of the auxiliary counter 3 is set to a level at which a high frequency output might be caused, a specific count is loaded to the auxiliary counter 3. An output terminal 10 of the auxiliary counter 3 is kept to the same level until a specific number of clock inputs 9 is counted after the count is loaded. The OR circuit 4 allows the output of the synchronous counter 2 to take prescedence over the output of the auxiliary counter 3 and the lower limit is compensated at the output terminal for the pulse width of a high frequency output only.
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