| 摘要 |
PURPOSE:To set optionally a slice level by generating a slice signal with respect to each of half waves of an input signal and inverting the polarity of one slice signal and adding slice signals. CONSTITUTION:A signal (a) inputted from an input terminal 11 is outputted as currents (b) and (c) having current waveforms of polarities opposite to each other by current output circuits 12 and 13. The output of the detecting circuit 12 is supplied to the emitter of a transistor TR16, and voltages of voltage sources 18 and 20 are set properly, and thereby, a sliced signal (d) is outputted from the collector of the TR16. Meanwhile, the output of the detecting circuit 13 is supplied to the emitter of a TR17, and voltages of voltage sources 19 and 21 are set properly, and thereby, a sliced signal (e) is outputted from the collector of the TR17. In an adding circit 22, signals (d) and (e) are added after inverting the polarity of one of them. Thus, the slice level is set optionally. |
