发明名称 PIN ACCESS CIRCUIT FOR PACKAGE TESTING MACHINE
摘要 PURPOSE:To attain to shorten an inspection time, by performing the input and output indication of a pin, the input and output of data and the judgement of an error in synchronous relation to one test clock. CONSTITUTION:Three informations of an input output indication signal S-1 for determining the input and output of a test pin 2, a mask signal S-2 for controlling an error flag signal S-6 and a data signal S-3 are stored in a pattern memory part 1 and signals S-1, S-2, S-3 pass through a pattern transmission part 3 in the timing of a test clock signal S-4 to be sent out to a signal control part 4 and a signal judge part 5. At first, when the signal S-1 is output indication, the signal S-3 is sent out to the judge part 5 and the signal S-3 sent out to the pin 2 is compared with the signal transmitted to the judge part 5 through the control part 4 as a signal S-5 to receive self-check. Next, when the signal S-1 is input indication, the signal S-3 is sent out to the judge part 5 and, at this time, the signal S-5 is sent out the judge part 5 through the pin 2 and the control part 4 to receive comparison and judgement. If the signal S-6 is not masked by S-2, it is outputted from the judge part 5.
申请公布号 JPS60219570(A) 申请公布日期 1985.11.02
申请号 JP19840075963 申请日期 1984.04.16
申请人 NIPPON DENKI KK 发明人 NAKAYAMA AKIHISA
分类号 G01R31/28;G01R31/317 主分类号 G01R31/28
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