| 摘要 |
PURPOSE:To attain the miniaturization and low power consumption by using a memory circuit which stores the timing information and the control information in different addresses and reading out both of said information successively. CONSTITUTION:A memory circuit 3 delivers the timing information t1 by an address a1, and a comparator 4 delivers a coincidence pulse 14 to a control circuit 5 when the value of an output signal 13 of a frame counter circuit 1 is set at t1. The circuit 5 delivers the first address counter clock pulse 15 to an address counter circuit 2 when the pulse 14 is supplied. The value of an address signal 12 is equal to an address a2. A latch circuit 6 reads the control information c1 by a latch pulse 16 and holds it until the next pulse 16 is supplied. The circuit 2 sets the value of an address signal 12 at a3 by the second address counter clock pulse 15. Thus the circuit 3 delivers the timing information t2. |
