| 摘要 |
PURPOSE:To avoid a malfunction of a circuit at the next stage when a PLL fetches no signal by actuating a swtich to deliver no output when no signal is fetched. CONSTITUTION:Whether or not a PLL fetches signals can be decided by checking an output LOCK. An AND gate 10 obtains an OR of the LOCK and the output of a counter 6 and delivers it. Thus f0 or a signal frequency is delivered when the PLL fetches signals. While a direct current (level 0) is delivered when the PLL fetches signals. Therefore the circuit of the next stage has no malfunction just with reference to frequencies. Furthermore a tristate gate, an analog switch, etc. can substitute the gate 10 to secure the same effect. |
