| 摘要 |
PURPOSE:To obtain a concrete circuit for deciding an erroneous location by means of the chain method by latching a numeral of a counter counting a clock of the same phase as a common clock of a shift register. CONSTITUTION:The error location is decided by applying sequentially a power alpha<j> or a root alpha of a generation polynomial as a variable of an error location polynomial x<2>+sigma1x+sigma2 and detecting that the polynomial becomes zero in the decoding of the Reed Solomon code having two-symbol error correction capability. In this case, three registers 1, 2, 3 driven by the common clock are provided, the 1st register is constituted as a shift circuit feeding back the result to an input via a ROM to which alpha0=1 is preset and having a constant multiplied by alpha<2>, the 2nd register is constituted as a shift circuit feeding back the result to the input via a ROM to which sigma1 is preset and having a constant multiplied by alpha and the 3rd register is constituted as a shift circuit inputting sigma2 as it is, the output of the three shift circuits is synthesized sequentially at each bit and the circuit detecting the bit of the synthesis output being zero detects the code error bit location.
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