发明名称 STORAGE DEVICE ADDRESS CONTROL SYSTEM
摘要 PURPOSE:To improve the economical efficiency of a computer or the like by using one address register for both the specification of a storage device address and a byte position in a buffer. CONSTITUTION:A writing address register is constituted of a high-order address register 11-1 holding a high-order digit part and a low-order address register 11-2 holding a low-order digit part. An output 30 from the low-order address register 11-2 specifies the byte position of the buffer 18 storing the output byte of a data processing part 17. The register 11-2 is counted up in each byte processing through an increment circuit 32. A carried value from the most significant digit at the increment operation of the register 11-2 is held by a carrying holding circuit 34 constituted of a flip flop and having an object to delay the carrying. Therefore, the carried value can be prevented from being immediately transmitted to the upper address register 11-1 and changed at its contents.
申请公布号 JPS60218146(A) 申请公布日期 1985.10.31
申请号 JP19840074320 申请日期 1984.04.13
申请人 FUJITSU KK 发明人 BABA NOBUYUKI
分类号 G06F9/34;G06F12/02 主分类号 G06F9/34
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