发明名称 INPUT/OUTPUT CONTROL SYSTEM
摘要 PURPOSE:To attain the connection to a channel without giving adverse effect on the operation of other I/O even when an I/O with slow start processing is connected by issuing a start indication to other I/O while start indication is fed to one I/O. CONSTITUTION:When an input/output channel 1 receives an input/output instruction from a CPU, the channel 1 selects an I/O 3-0 by using a common interface line 4 and transmits the start instruction. Then the channel 1 selects a sub- channel 2-0, sets the control state of the present I/O 3-0 to a control information field by I/O, and a timer start line 11 starts stepwise a supervisory timer field for the corresponding time of the sub-channel 2-0. When the end of operation is generated in an I/O 3-1 in this case, the end of operation is informed to the channel 1 via a status line 6-1. The channel 1 selects the I/O 3-1 via the common line 4, reads the end status so as to attain end processing. When the command chain is satisfied, the start is commanded further to the I/O 3-1.
申请公布号 JPS60217447(A) 申请公布日期 1985.10.31
申请号 JP19840072779 申请日期 1984.04.13
申请人 HITACHI SEISAKUSHO KK 发明人 OOSAKA HIROSHI
分类号 G06F13/12;(IPC1-7):G06F13/12 主分类号 G06F13/12
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