| 摘要 |
PURPOSE:To obtain a multiple accuracy floating point adding circuit having high speed at an operating speed, flexibility of the circuit and possibility of expansion by connecting plural single accuracy floating point adder circuits in cascade. CONSTITUTION:Four single accuracy floating decimal fractions are operated in parallel while being synchronized with the same clock and each single accuracy performs non-normalizing addition or normalizing operation once per one clock. For example, the executing procedure of 4-time accuracy floating point addition of two 4-time accuracy floating decimal fractions A=A1+A2+A3+A4, B= B1+B2+B3+B4 is 12 steps and no overlap exists between A1-A4, B1-B4. The four single accuracy floating decimals Q1, Q2, Q3, Q4 being the final result of the addition 12-step are 4-time accuracy floating decimal fractions normalized without overlap. Although the result of addition Q1+Q2+Q3+Q4 is not coincident with the sum A+B of the 4-time accuracy floating fractions being accurate inputs and it contains an error at the 2 or 3 bit of the least significant digit and it causes no problem. |
