| 摘要 |
PURPOSE:To detect the existence of data transferring from an opposite processor only by one instruction and to make it possible to transfer data by forming a program sequence control function to be actuated simultaneously with an interprocessor transfer instruction. CONSTITUTION:A transmission display F/F5 is set up by a transmission instruction 4 and a transmission display signal 6 is sent to a processor 2. A transfer register 16 latches a RAM output on the basis of the transmission instruction 4 and sends the data to an inter-processor data transfer line 17. At the execution of a received instruction 19, a reception display F/F9 is raised by the received instruction 19, and a reception display signal 10 is sent. At the end timing of the received instruction 19, a signal 22 for resetting the opposite transmission display F/F5 is sent through a delay circuit 20 and a differential circuit 21. The received instruction 19 controls an address control circuit 25 through a sequence control circuit 24. On the basis of the status of the opposite transmission display signal 6, a sequential address in a sequence control circuit 24 or a jump address 26 is sent. |
