| 摘要 |
PURPOSE:To simplify the circuit demodulating which identifies ''1'' from ''0'' for demodulation by reproducing a synchronizing clock pulse at the reception side and using it so as to sample a modulation signal. CONSTITUTION:A clock pulse reproducing device 20 reproduces a clock pulse from a clock signal of an oscillator 12 and an output of a leading edge detector 14. The clock pulse is a pulse rising at the trailing of the leading edge pulse and also a pulse falling at a half of the reception signal and when the pulse is given to a shift register 16 as a shift pulse, the register 16 stores the reception signal. Since the reception signal in this case by using a modulation pulse in which a time of the level at H to data 1, 0 shares respectively 3/4 and 1/4 of one bit's share and also the reception signal is inputted to the register 16 by a sampling pulse delayed by 1/2-bit from the leading as mentioned above, the signal is demodulated easily. |
