| 摘要 |
PURPOSE:To obtain a timing pulse with high accuracy by controlling the count of a frequency divider in response to a phase difference between an input signal and a 1/2N frequency-division output of a stable synchronizing signal having 2N times frequency to eliminate the phase jitter. CONSTITUTION:An input signal (a) of a frequency Fi and a signal (e) of a frequency Fr are fed to a phase detector 1. An output (b) of the phase detector 1 is inputted to a period counter 4 and a counter gate 2. When the output (b) is at an Hi level, an external synchronizing signal in the frequency 2NFr passes through the counter gate 2. An output (c) of the counter gate 2 is generated in response to the phase difference between the signals (a) and (e). A clock counter 3 counts signals by 2<m> periods' share and an m-bit shift parallel output is obtained as the counter output. The output and a theoretical set value N are compared by a tri-state output comparator 6. The output of the comparator 6 is inputted to a frequency divider 7 to control the coefficient. |
