LSI-Microcomputer.

摘要

The present invention discloses an integrated circuit having a data bus (42), an address bus (41), a processor (2) and a memory (3) each connected to the data bus (42) and the address bus (41), a first transmitter (64) for transmitting data inputted to a data terminal (91) to the data bus (42), a second transmitter (71) for transmitting data on the data bus (42) to the data terminal (91), a third transmitter (65) for transmitting an address inputted to an address terminal (92) to the address bus (41 and signal generate means (5) for generating signals to set the respective outputs from the first and third transmitters (64, 65) to the high impedance in response to a memory read request supplied from the processor (2), for generating signals to set the respective outputs from a data output of memory module to transmit data from the memory (3) to the data bus (42), the first transmitter (64), and the third transmitter (65) to the high impedance in response to a memory write request, for generating signals to set the respective outputs from a data output of processor module and an address output of processor module to output data and an address from the processor (2) to the data bus (42) and the address bus (41), respectively to the high impedance in response to a memory read request from an external device, and for generating signals to set the respective outputs from the data output of processor module and the address output of processor module in response to a memory write request from an external device, the integrated circuit further including a fourth transmitter (72) for transmitting an address on the address bus (41) to the address terminal (92); wherein the signal generate means generates signals to set the outputs from the first and third transmitters (64, 65) to the high impedance in response to an external memory read request supplied from the processor (2), sets the respective outputs from the data output of memory module, the first transmitter (64), and the third transmitter (65) to the high impedance in response to an external memory write request supplied from the processor (2), and responds to the read or write request from the external device in preference to the read or write request from the processor (2).