| 摘要 |
<p>23 Display apparatus includes a microcomputer, a multi-digit seven-segment display module, and a decoding addressable latch device. The segment inputs of the display module are connected through a buffer to microcosmputer output lines to permit the microcomputer to generate seven-segment code. The address inputs of the latch device are connected to the same microcomputer output lines, and the output lines of the latch are connected through a buffer to digit select line of the display device. The microcomputer first generates a digit select address code which is supplied to the latch inputs and frozen there by microcomputer actuation of the latch ENABLE input. This causes the latch to latchably energize the specified digit select line, and the microcomputer outputs the seven-segment code of the desired display character to the segment inputs of the display module. By connecting the latch address inputs and display module segment inputs in parallel, the apparatus provides micro computer generation of the seven-segment code while reducing the number of microcomputer output lines required. Objectionable effects of "ghost" energization of undesired segments caused by multiplexing latch address information and display data are minimized by selection of the multiplexed segments according to predetermined criteria, and by deenergizing all segments of all digits when blank character is to be displayed.</p> |
