| 摘要 |
PCT No. PCT/JP80/00169 Sec. 371 Date Mar. 25, 1981 Sec. 102(e) Date Mar. 20, 1981 PCT Filed Jul. 24, 1980 PCT Pub. No. WO81/00321 PCT Pub. Date Feb. 5, 1981.A data processing system having hierarchical memories comprised of buffer memories contained in a plurality of central processing units, an intermediate buffer memory and a main memory having a plurality of banks. The intermediate buffer memory and the main memory are controlled under both a swap control method and a set associative control method. These two memories are accessed by address information which includes both bank-selection address bits and set-selection address bits. The bank-selection address bits are partially modified by part of the set-selection address bits.
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