发明名称 CENTRAL PROCESSOR
摘要 PURPOSE:To decrease the word width which gives access to an address area of a ROM, for example, which receives an access immediately after it is reset, by setting different word widths when access is given to each area of plural divided address spaces. CONSTITUTION:A CPU10 is connected with an external bus 50, and a RAM3 and a magnetic disk device 4 have the 32-bit word width respectively. While a ROM20 has the 8-bit word width and is connected only to the lower 8 bits of the bus 50. Both the instruction length and the data length of the CPU10 are variable every 8 bits, and the memory addresses are allocated for every 8 bits. The CPU10 is kept in a state A immediately after it is reset and gives an access with 8-bit data width to the ROM20 which is allocated to an area forming a part of an area within a memory address space. At the same time, the CPU10 gives access with 32 bits to other areas of the RAM3 to be allocated. While the accesses are all carried out with 32-bit data width in a state B.
申请公布号 JPS60215260(A) 申请公布日期 1985.10.28
申请号 JP19840073255 申请日期 1984.04.10
申请人 MITSUBISHI DENKI KK 发明人 NAKAMURA KAZUO
分类号 G06F13/16;G06F12/04;G06F12/06 主分类号 G06F13/16
代理机构 代理人
主权项
地址