| 摘要 |
PURPOSE:To easily count the number of parallel input pulses consisting of the optional number of bits by providing a full-adder which adds the output of input pulses summed up in parallel and an addend inputted after the output of an addition result is delayed by one bit. CONSTITUTION:An N-bit parallel input adder 5 counts N-bit parallel pulses inputted synchronously with a clock signal CLK as a K-bit sum. This sum is inputted to the full-adder 7, which inputs the output of an FF8 as an addend and adds it to the output of the adder 5, bit by bit. The result is stored in the FF8 for every clock. Thus, the full adder 7 sums up the output of the adder 5 and outputs a carry output to a carry pulse output circuit 10. The circuit 10 outputs a carry pulse to a counter circuit 11 synchronously with the clock signal CLK and the circuit 11 counts the input carry pulse. Consequently, the total number of parallel input pulses of the optional number of bits is obtained in a short time. |
