| 摘要 |
PURPOSE:To reduce a penetration current by constituting the complementary gate circuit by connecting gates of an N and a PIGFET to drains of an N and a PIGFET whose sources are connected to an input terminal and then connecting the common drain of the former N and PIGFETs to an output terminal. CONSTITUTION:An input signal from a terminal 5 is applied to sources of N and PIGFETs Q3 and Q5, whose outputs are inputted to gates of N and PIGFETs Q4 and Q6 to obtain the output of the common drain at a terminal 8. The time when the FETs Q6 and Q4 are both on is the period from the ''L'' level to the ''H'' level of the input to the terminal 5 and a penetration current flows only in this period. This period is right before the FETQ4 turns on right before the FETQ6 turns off and the penetration current flowing from the FETQ6 to the FETQ4 is small. Further, almost no penetration current flows in the transition of the input signal from the ''H'' level to the ''L'' level because the FETQ6 begins to turn on and the FETQ4 begins to turn off nearly at the same time. |
