发明名称 ANALOG MULTIPLIER IMPROVED IN LINEARITY
摘要 An analog multiplier circuit for multiplying X and Y input voltage signals and using two differential amplifiers to produce a multiplied output, in which separate pairs of transistors provide base drive currents to the amplifier transistors, one pair being associated with each amplifier. Trimming voltages are applied between the bases of each transistor pair to independently adjust the base voltage offsets. Nonlinearities between the multiplier output and the X input are reduced by appropriate trimming of the transistor base voltage differentials. Each of the differential amplifier transistors has a common base connection with a matching transistor that carries a current which is complementary to the amplifier transistor current with respect to the Y input signal, thereby reducing output nonlinearities with respect to the Y input signal by making the total base drive currents of both transistors substantially independent of the Y voltage signal. Separate current sources also supply the standing base currents for the transistors of one of the amplifiers, thereby correcting for static imbalances in the base drive circuitry.
申请公布号 JPS60214612(A) 申请公布日期 1985.10.26
申请号 JP19840173986 申请日期 1984.08.21
申请人 PURESHIJIYON MONORISHITSUKUSU INC 发明人 DEREKU EFU BOUAAZU
分类号 G06G7/163 主分类号 G06G7/163
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