发明名称 RECEIVING AND ANALYZING CIRCUIT FOR VARIABLE LENGTH DATA
摘要 PURPOSE:To increase a processing speed and improve functions by adding a data analyzing device to a data receiving circuit, deciding on the significance of data and its length, and reporting the analytic result to a data processing circuit only when significant data is received. CONSTITUTION:One-word data received by the data receiving circuit 1 is outputted to a buffer register 3 and supplied to address inputs A2 and A3 of an analytic memory 6. This memory 6 is so programmed as to output decoding outputs D2 and D3 indicating received data analytic results corresponding to address inputs A0-A3. Here, the D2 shows with ''1'' that significant data is received and the D3 outputs ''1'' only when the 1st word is 01 and the 2nd word is 01. The reception report of the significant data is outputted from an analytic result output circuit 8 to a data processing circuit 10 on the basis of the outputs D2 and D3. Thus, only significant data is extracted from received data whose length is variable and starting is performed by the data processing part.
申请公布号 JPS60214660(A) 申请公布日期 1985.10.26
申请号 JP19840072132 申请日期 1984.04.11
申请人 NIPPON DENKI KK 发明人 KIYASU HIDETO
分类号 H04L29/02;H04L13/18 主分类号 H04L29/02
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